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| author | David S. Miller <davem@davemloft.net> | 2006-02-27 05:37:41 +0100 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 10:14:06 +0100 |
| commit | 97c4b6f95afadea5846b78ce589d25de2a245c56 (patch) | |
| tree | 11110547d3c92657ae8199f039e35c3a74d32107 /include/asm-sparc64 | |
| parent | [SPARC64]: Avoid dcache-dirty page state management on sun4v. (diff) | |
| download | linux-97c4b6f95afadea5846b78ce589d25de2a245c56.tar.xz linux-97c4b6f95afadea5846b78ce589d25de2a245c56.zip | |
[SPARC64]: Use 13-bit context size always.
We no longer have the problems that require using the smaller
sizes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64')
| -rw-r--r-- | include/asm-sparc64/mmu.h | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h index 1504d303a1d5..da14a9bf0ed6 100644 --- a/include/asm-sparc64/mmu.h +++ b/include/asm-sparc64/mmu.h @@ -6,19 +6,7 @@ #include <asm/const.h> #include <asm/hypervisor.h> -/* - * For the 8k pagesize kernel, use only 10 hw context bits to optimize some - * shifts in the fast tlbmiss handlers, instead of all 13 bits (specifically - * for vpte offset calculation). For other pagesizes, this optimization in - * the tlbhandlers can not be done; but still, all 13 bits can not be used - * because the tlb handlers use "andcc" instruction which sign extends 13 - * bit arguments. - */ -#if PAGE_SHIFT == 13 -#define CTX_NR_BITS 10 -#else -#define CTX_NR_BITS 12 -#endif +#define CTX_NR_BITS 13 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL)) |