diff options
| author | Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> | 2005-10-31 00:00:07 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-10-31 02:37:16 +0100 |
| commit | 96d55b882b85b26711a06d8fb2c901df9d52a48b (patch) | |
| tree | 309b8993ad321c050411a8dd74729180488a5dcc /include/asm-um/cache.h | |
| parent | [PATCH] m32r: SMC91x driver update (diff) | |
| download | linux-96d55b882b85b26711a06d8fb2c901df9d52a48b.tar.xz linux-96d55b882b85b26711a06d8fb2c901df9d52a48b.zip | |
[PATCH] uml: reuse i386 cpu-specific tuning
Make UML share the underlying cpu-specific tuning done on i386.
Actually, for now many config options aren't used a lot - but that can be done
later. Also, UML relies on GCC optimization for things like memcpy and such
more than i386, so specifying the correct -march and -mtune should be enough.
Later, we may want to correct some other stuff.
For instance, since FPU context switching, for us, is done (at least
partially, i.e. between our kernelspace and userspace) by the host, we may
allow usage of FPU operations by GCC. This doesn't hold for kernelspace vs.
kernelspace, but we don't support preemption.
Signed-off-by: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-um/cache.h')
| -rw-r--r-- | include/asm-um/cache.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/include/asm-um/cache.h b/include/asm-um/cache.h index 4b134fe8504e..a10602a5b2d6 100644 --- a/include/asm-um/cache.h +++ b/include/asm-um/cache.h @@ -1,10 +1,21 @@ #ifndef __UM_CACHE_H #define __UM_CACHE_H -/* These are x86 numbers */ -#define L1_CACHE_SHIFT 5 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#include <linux/config.h> -#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ +#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT) +# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) +#elif defined(CONFIG_UML_X86) /* 64-bit */ +# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ +#else +/* XXX: this was taken from x86, now it's completely random. Luckily only + * affects SMP padding. */ +# define L1_CACHE_SHIFT 5 +#endif + +/* XXX: this is valid for x86 and x86_64. */ +#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #endif |