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authorThomas Gleixner <tglx@linutronix.de>2007-10-11 11:20:03 +0200
committerThomas Gleixner <tglx@linutronix.de>2007-10-11 11:20:03 +0200
commit96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42 (patch)
treed947a467aa2da3140279617bc4b9b101640d7bf4 /include/asm-x86/cache_64.h
parentx86: sanitize pathes arch/x86/kernel/cpu/Makefile (diff)
downloadlinux-96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42.tar.xz
linux-96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42.zip
i386/x86_64: move headers to include/asm-x86
Move the headers to include/asm-x86 and fixup the header install make rules Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/cache_64.h')
-rw-r--r--include/asm-x86/cache_64.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/include/asm-x86/cache_64.h b/include/asm-x86/cache_64.h
new file mode 100644
index 000000000000..052df758ae61
--- /dev/null
+++ b/include/asm-x86/cache_64.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-x86_64/cache.h
+ */
+#ifndef __ARCH_X8664_CACHE_H
+#define __ARCH_X8664_CACHE_H
+
+
+/* L1 cache line size */
+#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+#ifdef CONFIG_X86_VSMP
+
+/* vSMP Internode cacheline shift */
+#define INTERNODE_CACHE_SHIFT (12)
+#ifdef CONFIG_SMP
+#define __cacheline_aligned_in_smp \
+ __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT)))) \
+ __attribute__((__section__(".data.page_aligned")))
+#endif
+
+#endif
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+#endif