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authorJeremy Fitzhardinge <jeremy@goop.org>2008-07-11 01:22:56 +0200
committerIngo Molnar <mingo@elte.hu>2008-07-11 15:44:57 +0200
commit8d28aab59fe939be40efae870ced0b05caa259fb (patch)
tree63cbe1eb47521a9005d98c695d44c4ab480730d3 /include/asm-x86/cpufeature.h
parentx86: fix tsc unification buglet with ftrace and stackprotector (diff)
downloadlinux-8d28aab59fe939be40efae870ced0b05caa259fb.tar.xz
linux-8d28aab59fe939be40efae870ced0b05caa259fb.zip
x86_64: add pseudo-features for 32-bit compat syscall
Add pseudo-feature bits to describe whether the CPU supports sysenter and/or syscall from ia32-compat userspace. This removes a hardcoded test in vdso32-setup. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/cpufeature.h')
-rw-r--r--include/asm-x86/cpufeature.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 84a56da397b1..75ef959db329 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -74,8 +74,8 @@
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
-/* 14 free */
-/* 15 free */
+#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
+#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */