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authorAustin Zhang <austin_zhang@linux.intel.com>2008-08-25 17:14:51 +0200
committerIngo Molnar <mingo@elte.hu>2008-08-25 17:28:16 +0200
commit2a61812af2e564cba2c8170cf96e1c823210f619 (patch)
tree7d8656e0d7b673ac0550c231d510b11a6e4441f8 /include/asm-x86/cpufeature.h
parentx86: fix cpufreq + sched_clock() regression (diff)
downloadlinux-2a61812af2e564cba2c8170cf96e1c823210f619.tar.xz
linux-2a61812af2e564cba2c8170cf96e1c823210f619.zip
x86: add X86_FEATURE_XMM4_2 definitions
Added Intel processor SSE4.2 feature flag. No in-tree user at the moment, but makes the tree-merging life easier for the crypto tree. Signed-off-by: Austin Zhang <austin.zhang@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/cpufeature.h')
-rw-r--r--include/asm-x86/cpufeature.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 2f5a792b0acc..762f6a6bc707 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -91,6 +91,7 @@
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
@@ -189,6 +190,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
+#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
# define cpu_has_invlpg 1