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authorvenkatesh.pallipadi@intel.com <venkatesh.pallipadi@intel.com>2008-03-19 01:00:14 +0100
committerIngo Molnar <mingo@elte.hu>2008-04-17 17:41:19 +0200
commit2e5d9c857d4e6c9e7b7d8c8c86a68a7842d213d6 (patch)
tree6c90c0f9f38ff85e2f42ddc0f4ef0291cdd47d38 /include/asm-x86/msr-index.h
parentx86: PAT documentation (diff)
downloadlinux-2e5d9c857d4e6c9e7b7d8c8c86a68a7842d213d6.tar.xz
linux-2e5d9c857d4e6c9e7b7d8c8c86a68a7842d213d6.zip
x86: PAT infrastructure patch
Sets up pat_init() infrastructure. PAT MSR has following setting. PAT |PCD ||PWT ||| 000 WB _PAGE_CACHE_WB 001 WC _PAGE_CACHE_WC 010 UC- _PAGE_CACHE_UC_MINUS 011 UC _PAGE_CACHE_UC We are effectively changing WT from boot time setting to WC. UC_MINUS is used to provide backward compatibility to existing /dev/mem users(X). reserve_memtype and free_memtype are new interfaces for maintaining alias-free mapping. It is currently implemented in a simple way with a linked list and not optimized. reserve and free tracks the effective memory type, as a result of PAT and MTRR setting rather than what is actually requested in PAT. pat_init piggy backs on mtrr_init as the rules for setting both pat and mtrr are same. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/msr-index.h')
-rw-r--r--include/asm-x86/msr-index.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index 3ed97144c07b..af4e07f661b8 100644
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -57,6 +57,8 @@
#define MSR_MTRRfix4K_F8000 0x0000026f
#define MSR_MTRRdefType 0x000002ff
+#define MSR_IA32_CR_PAT 0x00000277
+
#define MSR_IA32_DEBUGCTLMSR 0x000001d9
#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
#define MSR_IA32_LASTBRANCHTOIP 0x000001dc