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| author | Arjan van de Ven <arjan@linux.intel.com> | 2008-10-17 18:20:26 +0200 |
|---|---|---|
| committer | Arjan van de Ven <arjan@linux.intel.com> | 2008-10-17 18:20:26 +0200 |
| commit | 651dab4264e4ba0e563f5ff56f748127246e9065 (patch) | |
| tree | 016630974bdcb00fe529b673f96d389e0fd6dc94 /include/asm-x86/msr-index.h | |
| parent | DECLARE_PER_CPU needs linux/percpu.h (diff) | |
| parent | {pci,pnp} quirks.c: don't use deprecated print_fn_descriptor_symbol() (diff) | |
| download | linux-651dab4264e4ba0e563f5ff56f748127246e9065.tar.xz linux-651dab4264e4ba0e563f5ff56f748127246e9065.zip | |
Merge commit 'linus/master' into merge-linus
Conflicts:
arch/x86/kvm/i8254.c
Diffstat (limited to 'include/asm-x86/msr-index.h')
| -rw-r--r-- | include/asm-x86/msr-index.h | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h index 44bce773012e..dabd10f0bbee 100644 --- a/include/asm-x86/msr-index.h +++ b/include/asm-x86/msr-index.h @@ -1,5 +1,5 @@ -#ifndef __ASM_MSR_INDEX_H -#define __ASM_MSR_INDEX_H +#ifndef ASM_X86__MSR_INDEX_H +#define ASM_X86__MSR_INDEX_H /* CPU model specific register (MSR) numbers */ @@ -176,6 +176,10 @@ #define MSR_IA32_TSC 0x00000010 #define MSR_IA32_PLATFORM_ID 0x00000017 #define MSR_IA32_EBL_CR_POWERON 0x0000002a +#define MSR_IA32_FEATURE_CONTROL 0x0000003a + +#define FEATURE_CONTROL_LOCKED (1<<0) +#define FEATURE_CONTROL_VMXON_ENABLED (1<<2) #define MSR_IA32_APICBASE 0x0000001b #define MSR_IA32_APICBASE_BSP (1<<8) @@ -310,4 +314,19 @@ /* Geode defined MSRs */ #define MSR_GEODE_BUSCONT_CONF0 0x00001900 -#endif /* __ASM_MSR_INDEX_H */ +/* Intel VT MSRs */ +#define MSR_IA32_VMX_BASIC 0x00000480 +#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 +#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 +#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 +#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 +#define MSR_IA32_VMX_MISC 0x00000485 +#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 +#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 +#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 +#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 +#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a +#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b +#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c + +#endif /* ASM_X86__MSR_INDEX_H */ |