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author | Ingo Molnar <mingo@elte.hu> | 2008-09-24 10:31:34 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-09-24 10:31:34 +0200 |
commit | e6aa0f07cb5e81a7cbeaf3be6e2101234c2f0d30 (patch) | |
tree | 77926550ac0c31b1423bcf193a4ed0ecb7fda2c1 /include/asm-x86/processor.h | |
parent | x86, microcode rework, v2, renaming cont. (diff) | |
parent | Linux 2.6.27-rc7 (diff) | |
download | linux-e6aa0f07cb5e81a7cbeaf3be6e2101234c2f0d30.tar.xz linux-e6aa0f07cb5e81a7cbeaf3be6e2101234c2f0d30.zip |
Merge commit 'v2.6.27-rc7' into x86/microcode
Diffstat (limited to 'include/asm-x86/processor.h')
-rw-r--r-- | include/asm-x86/processor.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index 58a76f69ee31..c63a47651890 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -693,6 +693,29 @@ extern unsigned long boot_option_idle_override; extern unsigned long idle_halt; extern unsigned long idle_nomwait; +/* + * on systems with caches, caches must be flashed as the absolute + * last instruction before going into a suspended halt. Otherwise, + * dirty data can linger in the cache and become stale on resume, + * leading to strange errors. + * + * perform a variety of operations to guarantee that the compiler + * will not reorder instructions. wbinvd itself is serializing + * so the processor will not reorder. + * + * Systems without cache can just go into halt. + */ +static inline void wbinvd_halt(void) +{ + mb(); + /* check for clflush to determine if wbinvd is legal */ + if (cpu_has_clflush) + asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); + else + while (1) + halt(); +} + extern void enable_sep_cpu(void); extern int sysenter_setup(void); |