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| author | Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> | 2005-11-05 17:25:54 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-11-15 04:55:17 +0100 |
| commit | bf0f2e23834e2bf7d64b467ef07095b1c7e2c04b (patch) | |
| tree | 0a652a8e4cc51f50139d892cee17f7a699c4afa4 /include/asm-x86_64/pgalloc.h | |
| parent | [PATCH] x86_64: Remove asm-x86_64/rwsem.h (diff) | |
| download | linux-bf0f2e23834e2bf7d64b467ef07095b1c7e2c04b.tar.xz linux-bf0f2e23834e2bf7d64b467ef07095b1c7e2c04b.zip | |
[PATCH] x86_64: Set ____cacheline_maxaligned_in_smp alignment to 128 bytes
The current value was correct before the introduction of Intel EM64T support -
but now L1_CACHE_SHIFT_MAX can be less than L1_CACHE_SHIFT, which _is_ funny!
Between the few users of ____cacheline_maxaligned_in_smp, we also have (for
example) rcu_ctrlblk, and struct zone, with zone->{lru_,}lock. I.e. we have
a lot of excess cacheline bouncing on them.
No correctness issues, obviously. So this could even be merged for 2.6.14
(I'm not a fan of this idea, though).
CC: Andi Kleen <ak@suse.de>
Signed-off-by: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64/pgalloc.h')
0 files changed, 0 insertions, 0 deletions