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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2016-09-09 15:07:15 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2016-09-09 16:03:29 +0200 |
| commit | 9dbd5bb25c56e35e6b4c34d968689a1ded850924 (patch) | |
| tree | f81f727180de3d8eef52c1d69d72a46cc196eea5 /include/drm/drm_cache.h | |
| parent | arm64: Introduce raw_{d,i}cache_line_size (diff) | |
| download | linux-9dbd5bb25c56e35e6b4c34d968689a1ded850924.tar.xz linux-9dbd5bb25c56e35e6b4c34d968689a1ded850924.zip | |
arm64: Refactor sysinstr exception handling
Right now we trap some of the user space data cache operations
based on a few Errata (ARM 819472, 826319, 827319 and 824069).
We need to trap userspace access to CTR_EL0, if we detect mismatched
cache line size. Since both these traps share the EC, refactor
the handler a little bit to make it a bit more reader friendly.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'include/drm/drm_cache.h')
0 files changed, 0 insertions, 0 deletions