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author | Jani Nikula <jani.nikula@intel.com> | 2015-02-25 13:46:53 +0100 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-10 09:59:32 +0100 |
commit | 0e71244c1bb873f0e3be3b79d3436d7ef2601029 (patch) | |
tree | 35ee79262d5284038745bf6417daa7553a4b5ed9 /include/drm/drm_dp_helper.h | |
parent | drm/dp: indentation and ordering cleanups (diff) | |
download | linux-0e71244c1bb873f0e3be3b79d3436d7ef2601029.tar.xz linux-0e71244c1bb873f0e3be3b79d3436d7ef2601029.zip |
drm/dp: add DPCD definitions from eDP 1.2
Mostly display control related DPCD addresses.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/drm/drm_dp_helper.h')
-rw-r--r-- | include/drm/drm_dp_helper.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 98fefe45d158..a3ecaa06c9db 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -341,6 +341,38 @@ #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ +#define DP_EDP_GENERAL_CAP_1 0x701 + +#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 + +#define DP_EDP_GENERAL_CAP_2 0x703 + +#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 + +#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 + +#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 +#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 + +#define DP_EDP_PWMGEN_BIT_COUNT 0x724 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 + +#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 + +#define DP_EDP_BACKLIGHT_FREQ_SET 0x728 + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f + +#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 +#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 + #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ |