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author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2019-01-23 03:32:27 +0100 |
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committer | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2019-01-23 12:56:32 +0100 |
commit | c25f0c6a0426527134d992bb4782cf5abdf962b6 (patch) | |
tree | 9ca9d36b5f72ea6e2efa3adb6e61482caf1435b2 /include/drm/i915_pciids.h | |
parent | drm/i915/sdvo: switch to kernel types (diff) | |
download | linux-c25f0c6a0426527134d992bb4782cf5abdf962b6.tar.xz linux-c25f0c6a0426527134d992bb4782cf5abdf962b6.zip |
drm/i915/icl: do a posting read after irq install
When reading GEN11_GT_INTR_DWx closely after enabling the interrupts
in gen11_irq_postinstall, the returned value is garbage. This can
cause other parts of the setup code (e.g. gen11_reset_one_iir) to
think that there are interrupts to be cleared when there are none.
The garbage value is only seen on the first read done after the enable,
so this looks like a posting issue. Adding a posting read after enabling
the interrupts does indeed fix the problem.
Note that the posting read has been purposely added outside of
gen11_master_intr_enable since the issue has only been observed when the
full interrupt setup is performed.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190123023227.8117-1-daniele.ceraolospurio@intel.com
Diffstat (limited to 'include/drm/i915_pciids.h')
0 files changed, 0 insertions, 0 deletions