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| author | Rahul Sharma <rahul.sharma@samsung.com> | 2014-03-12 15:56:46 +0100 |
|---|---|---|
| committer | Tomasz Figa <t.figa@samsung.com> | 2014-05-14 19:16:54 +0200 |
| commit | eefe119b81eb1afb6e815818ad119cdd2d442fd3 (patch) | |
| tree | 69e37fd063f6563a4c1522797b9bd74704272ca5 /include/dt-bindings/clock/exynos5260-clk.h | |
| parent | clk/samsung: add support for pll2550xx (diff) | |
| download | linux-eefe119b81eb1afb6e815818ad119cdd2d442fd3.tar.xz linux-eefe119b81eb1afb6e815818ad119cdd2d442fd3.zip | |
clk/samsung: add support for pll2650xx
Add support for pll2650xx in samsung pll file. This PLL variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock/exynos5260-clk.h')
0 files changed, 0 insertions, 0 deletions