diff options
| author | Vivek Gautam <gautam.vivek@samsung.com> | 2014-11-21 14:35:51 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2014-12-23 12:02:14 +0100 |
| commit | 83f191a7cdf5286a8f3745e847f50c29fa349da9 (patch) | |
| tree | 4e27f9a33d8b5e995f205a3b53e10e1d6638e2a6 /include/dt-bindings/clock/exynos7-clk.h | |
| parent | clk: samsung: exynos7: Add clocks for MSCL block (diff) | |
| download | linux-83f191a7cdf5286a8f3745e847f50c29fa349da9.tar.xz linux-83f191a7cdf5286a8f3745e847f50c29fa349da9.zip | |
clk: samsung: exynos7: Add required clock tree for USB
Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock/exynos7-clk.h')
| -rw-r--r-- | include/dt-bindings/clock/exynos7-clk.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 9f230da5f3d9..e33d0ca4c123 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -84,7 +84,14 @@ /* FSYS0 */ #define ACLK_MMC2 1 -#define FSYS0_NR_CLK 2 +#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 +#define ACLK_USBDRD300 3 +#define SCLK_USBDRD300_SUSPENDCLK 4 +#define SCLK_USBDRD300_REFCLK 5 +#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 +#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 +#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 +#define FSYS0_NR_CLK 9 /* FSYS1 */ #define ACLK_MMC1 1 |