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authorChao Xie <chao.xie@marvell.com>2015-04-30 03:53:42 +0200
committerStephen Boyd <sboyd@codeaurora.org>2015-06-04 21:07:53 +0200
commit24c65a02b23509284cce5185d81a150d699837b5 (patch)
treead6219b19da53757c6ab9ee699c89f2729f4895a /include/dt-bindings/clock/marvell,pxa168.h
parentclk: mmp: Fix the wrong factor table for uart PLL (diff)
downloadlinux-24c65a02b23509284cce5185d81a150d699837b5.tar.xz
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clk: mmp: add timer clock for pxa168/mmp2/pxa910
Timer has external fast clock, and it is a mux clock. Add the timer clock type for timer driver. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings/clock/marvell,pxa168.h')
-rw-r--r--include/dt-bindings/clock/marvell,pxa168.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h
index 84ce5de6c83d..3e45bdfe1aa4 100644
--- a/include/dt-bindings/clock/marvell,pxa168.h
+++ b/include/dt-bindings/clock/marvell,pxa168.h
@@ -18,6 +18,7 @@
#define PXA168_CLK_PLL1_13_1_5 18
#define PXA168_CLK_PLL1_2_1_5 19
#define PXA168_CLK_PLL1_3_16 20
+#define PXA168_CLK_PLL1_192 21
#define PXA168_CLK_UART_PLL 27
#define PXA168_CLK_USB_PLL 28
@@ -41,6 +42,7 @@
#define PXA168_CLK_SSP2 76
#define PXA168_CLK_SSP3 77
#define PXA168_CLK_SSP4 78
+#define PXA168_CLK_TIMER 79
/* axi periphrals */
#define PXA168_CLK_DFC 100