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authorSean Wang <sean.wang@mediatek.com>2018-03-01 04:27:50 +0100
committerStephen Boyd <sboyd@kernel.org>2018-03-19 21:25:09 +0100
commit55a5fcafe3a94e8a0777bb993d09107d362258d2 (patch)
treecbe1dd2e9155eff7d83d6f72cd3a6df055f6c782 /include/dt-bindings/clock/mt2701-clk.h
parentLinux 4.16-rc1 (diff)
downloadlinux-55a5fcafe3a94e8a0777bb993d09107d362258d2.tar.xz
linux-55a5fcafe3a94e8a0777bb993d09107d362258d2.zip
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
Just add binding for a fixed-factor clock axisel_d4, which would be referenced by PWM devices on MT7623 or MT2701 SoC. Cc: stable@vger.kernel.org Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings/clock/mt2701-clk.h')
-rw-r--r--include/dt-bindings/clock/mt2701-clk.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 551f7600ab58..24e93dfcee9f 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -176,7 +176,8 @@
#define CLK_TOP_AUD_EXT1 156
#define CLK_TOP_AUD_EXT2 157
#define CLK_TOP_NFI1X_PAD 158
-#define CLK_TOP_NR 159
+#define CLK_TOP_AXISEL_D4 159
+#define CLK_TOP_NR 160
/* APMIXEDSYS */