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| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-01-27 20:53:06 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-01-27 20:53:06 +0100 |
| commit | 195559506981c0a4c62397ad0220888324750070 (patch) | |
| tree | e58fc27d85c7d77c29a9b182b18d318040128f72 /include/dt-bindings/clock/qcom,gcc-msm8994.h | |
| parent | Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/... (diff) | |
| parent | clk: samsung: mark s3c...._clk_sleep_init() as __init (diff) | |
| download | linux-195559506981c0a4c62397ad0220888324750070.tar.xz linux-195559506981c0a4c62397ad0220888324750070.zip | |
Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY
- Exynos PLL code updates and overall minor clean-ups
* tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: mark s3c...._clk_sleep_init() as __init
clk: samsung: Add enable/disable support for PLL35XX clocks
clk: samsung: exynos5433: Correct typos in SoC name
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
Diffstat (limited to 'include/dt-bindings/clock/qcom,gcc-msm8994.h')
0 files changed, 0 insertions, 0 deletions