diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2020-01-14 08:24:26 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-12 22:47:14 +0200 |
| commit | c95854052558fdf0d6eef592effb5b1051c6eec1 (patch) | |
| tree | 6787e1b0689f58b917c9225abc8a39a9fa680243 /include/dt-bindings/clock/tegra30-car.h | |
| parent | dt-bindings: clock: tegra: Add clock ID for CSI TPG clock (diff) | |
| download | linux-c95854052558fdf0d6eef592effb5b1051c6eec1.tar.xz linux-c95854052558fdf0d6eef592effb5b1051c6eec1.zip | |
dt-bindings: clock: tegra: Remove PMC clock IDs
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so
these clocks should be provided by the Tegra PMC. IDs for these clocks
have been defined in dt-bindings/soc/tegra-pmc.h.
This patch removes the IDs for these clocks from the Tegra clock device
tree bindings.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings/clock/tegra30-car.h')
| -rw-r--r-- | include/dt-bindings/clock/tegra30-car.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 7b542c10fc27..f193663e6f28 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -232,11 +232,11 @@ #define TEGRA30_CLK_AUDIO3 204 #define TEGRA30_CLK_AUDIO4 205 #define TEGRA30_CLK_SPDIF 206 -#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ -#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ -#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ +/* 207 */ +/* 208 */ +/* 209 */ #define TEGRA30_CLK_SCLK 210 -#define TEGRA30_CLK_BLINK 211 +/* 211 */ #define TEGRA30_CLK_CCLK_G 212 #define TEGRA30_CLK_CCLK_LP 213 #define TEGRA30_CLK_TWD 214 @@ -262,9 +262,9 @@ /* 297 */ /* 298 */ /* 299 */ -#define TEGRA30_CLK_CLK_OUT_1_MUX 300 -#define TEGRA30_CLK_CLK_OUT_2_MUX 301 -#define TEGRA30_CLK_CLK_OUT_3_MUX 302 +/* 300 */ +/* 301 */ +/* 302 */ #define TEGRA30_CLK_AUDIO0_MUX 303 #define TEGRA30_CLK_AUDIO1_MUX 304 #define TEGRA30_CLK_AUDIO2_MUX 305 |