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| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-03 01:43:03 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-03 01:43:03 +0200 |
| commit | 5569aedf1dd82cc1e4d8d19f4424c2034583cb2a (patch) | |
| tree | e0246f3dce8356b66b1687688492273acd41d611 /include/dt-bindings/clock | |
| parent | Merge branch 'clk-hw-register' (early part) into clk-next (diff) | |
| parent | clk: rockchip: fix the rk3399 cifout clock (diff) | |
| download | linux-5569aedf1dd82cc1e4d8d19f4424c2034583cb2a.tar.xz linux-5569aedf1dd82cc1e4d8d19f4424c2034583cb2a.zip | |
Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:
A spelling fix and a bunch of rk3399 clock fixes.
* tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix the rk3399 cifout clock
clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
clk: rockchip: add some frequencies on the rk3399 PLL table
clk: rockchip: assign more necessary rk3399 clock ids
clk: rockchip: export some necessary rk3399 clock ids
clk: rockchip: rename rga clock-id on rk3399
clk: rockchip: add general gpu soft-reset on rk3399
clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/rk3399-cru.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index f60fe6e4b16e..50a44cffb070 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -72,7 +72,7 @@ #define SCLK_MACREF_OUT 106 #define SCLK_VOP0_PWM 107 #define SCLK_VOP1_PWM 108 -#define SCLK_RGA 109 +#define SCLK_RGA_CORE 109 #define SCLK_ISP0 110 #define SCLK_ISP1 111 #define SCLK_HDMI_CEC 112 @@ -129,6 +129,8 @@ #define SCLK_DPHY_TX0_CFG 163 #define SCLK_DPHY_TX1RX1_CFG 164 #define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 #define DCLK_VOP0 180 #define DCLK_VOP1 181 @@ -671,6 +673,7 @@ #define SRST_P_EDP_CTRL 285 /* cru_softrst_con18 */ +#define SRST_A_GPU 288 #define SRST_A_GPU_NOC 289 #define SRST_A_GPU_GRF 290 #define SRST_PVTM_GPU 291 |