diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2015-02-12 07:01:30 +0100 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2015-03-02 13:52:16 +0100 |
| commit | e654df7a1a4843429b5d1d6ee40cac9ecef75304 (patch) | |
| tree | 60111ee985afb8c61914d195af3c0d9a8e8f24ec /include/dt-bindings/clock | |
| parent | ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate (diff) | |
| download | linux-e654df7a1a4843429b5d1d6ee40cac9ecef75304.tar.xz linux-e654df7a1a4843429b5d1d6ee40cac9ecef75304.zip | |
ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the ipg clock's output. The MIPI DSI host
controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk -
the APB clock signal . In order to gate/ungate the ipg clock, this patch adds
a new shared clock gate named as "mipi_ipg".
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/imx6qdl-clock.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index dbc828c23a17..8780868458a0 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -250,6 +250,7 @@ #define IMX6QDL_CLK_GPT_3M 237 #define IMX6QDL_CLK_VIDEO_27M 238 #define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_END 240 +#define IMX6QDL_CLK_MIPI_IPG 240 +#define IMX6QDL_CLK_END 241 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ |