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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2017-06-21 15:29:15 +0200 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2017-06-23 10:14:57 +0200 |
| commit | e0de91a977bfe4c199138fa256a211a648ef6999 (patch) | |
| tree | c9d65f271815054bc821467366d2872b9e9cf4ac /include/dt-bindings/interrupt-controller | |
| parent | irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP (diff) | |
| download | linux-e0de91a977bfe4c199138fa256a211a648ef6999.tar.xz linux-e0de91a977bfe4c199138fa256a211a648ef6999.zip | |
irqchip/irq-mvebu-icu: Add new driver for Marvell ICU
The Marvell ICU unit is found in the CP110 block of the Marvell Armada
7K and 8K SoCs. It collects the wired interrupts of the devices located
in the CP110 and turns them into SPI interrupts in the GIC located in
the AP806 side of the SoC, by using a memory transaction.
Until now, the ICU was configured in a static fashion by the firmware,
and Linux was relying on this static configuration. By having Linux
configure the ICU, we are more flexible, and we can allocate dynamically
the GIC SPI interrupts only for devices that are actually in use.
The driver was initially written by Hanna Hawa <hannah@marvell.com>.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/dt-bindings/interrupt-controller')
| -rw-r--r-- | include/dt-bindings/interrupt-controller/mvebu-icu.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/dt-bindings/interrupt-controller/mvebu-icu.h b/include/dt-bindings/interrupt-controller/mvebu-icu.h new file mode 100644 index 000000000000..8249558545c7 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/mvebu-icu.h @@ -0,0 +1,15 @@ +/* + * This header provides constants for the MVEBU ICU driver. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H + +/* interrupt specifier cell 0 */ + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#endif |