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| author | Niravkumar L Rabara <niravkumar.l.rabara@intel.com> | 2023-08-01 03:02:31 +0200 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2023-08-08 13:32:34 +0200 |
| commit | 2a29fe831f80f6d9187e49a272d795f3d1b54cdb (patch) | |
| tree | 2c3b6899a495d0d0a9a398c1000e9b85ed502276 /include/dt-bindings/reset | |
| parent | dt-bindings: intel: Add Intel Agilex5 compatible (diff) | |
| download | linux-2a29fe831f80f6d9187e49a272d795f3d1b54cdb.tar.xz linux-2a29fe831f80f6d9187e49a272d795f3d1b54cdb.zip | |
dt-bindings: reset: add reset IDs for Agilex5
Add reset ID definitions required for Intel Agilex5 SoCFPGA, re-use
altr,rst-mgr-s10.h as common header file similar S10 & Agilex.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/altr,rst-mgr-s10.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h index 70ea3a09dbe1..04c4d0c6fd34 100644 --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h @@ -63,12 +63,15 @@ #define I2C2_RESET 74 #define I2C3_RESET 75 #define I2C4_RESET 76 -/* 77-79 is empty */ +#define I3C0_RESET 77 +#define I3C1_RESET 78 +/* 79 is empty */ #define UART0_RESET 80 #define UART1_RESET 81 /* 82-87 is empty */ #define GPIO0_RESET 88 #define GPIO1_RESET 89 +#define WATCHDOG4_RESET 90 /* BRGMODRST */ #define SOC2FPGA_RESET 96 |