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authorStephen Boyd <sboyd@codeaurora.org>2016-09-14 20:06:47 +0200
committerStephen Boyd <sboyd@codeaurora.org>2016-09-14 20:06:47 +0200
commit3db385ea144daea9c6e1a15f98eacafaec9ad9f1 (patch)
tree25316f2cb4f42674bcd127d3b812e17cbfe536eb /include/dt-bindings
parentclk: rk808: Pass the right pointer as the get_hw context (diff)
parentclk: samsung: Add support for EPLL on exynos5410 (diff)
downloadlinux-3db385ea144daea9c6e1a15f98eacafaec9ad9f1.tar.xz
linux-3db385ea144daea9c6e1a15f98eacafaec9ad9f1.zip
Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull samsung clk driver updates from Sylwester Nawrocki: In addition to a few clean up and code consolidation patches this includes: - addition of sound subsystem related clocks for Exynos5410 SoC (EPLL, PDMA) and support for "samsung,exynos5410-audss-clock" compatible in the clk-exynos-audss driver, - addition of DRAM controller related clocks for exynos5420, - MAINTAINERS update adding Chanwoo Choi as the Samsung SoC clock drivers co-maintainer. * tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Add support for EPLL on exynos5410 clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup clk: samsung: clk-exynos-audss: Add exynos5410 compatible clk: samsung: clk-exynos-audss: controller variant handling rework clk: samsung: Use common registration function for pll2550x clk: samsung: exynos5410: Expose the peripheral DMA gate clocks clk: samsung: exynos5420: Add clocks for CMU_CDREX domain clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code clk: samsung: exynos5260: Move struct samsung_cmu_info to init section MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos5410.h3
-rw-r--r--include/dt-bindings/clock/exynos5420.h11
-rw-r--r--include/dt-bindings/clock/exynos5440.h2
3 files changed, 15 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 85b467b3a207..6cb4e90f81fc 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -19,6 +19,7 @@
#define CLK_FOUT_MPLL 4
#define CLK_FOUT_BPLL 5
#define CLK_FOUT_KPLL 6
+#define CLK_FOUT_EPLL 7
/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128
@@ -55,6 +56,8 @@
#define CLK_MMC0 351
#define CLK_MMC1 352
#define CLK_MMC2 353
+#define CLK_PDMA0 362
+#define CLK_PDMA1 363
#define CLK_USBH20 365
#define CLK_USBD300 366
#define CLK_USBD301 367
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 17ab8394bec7..6fd21c291416 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -214,6 +214,9 @@
#define CLK_MOUT_SW_ACLK400 651
#define CLK_MOUT_USER_ACLK300_GSCL 652
#define CLK_MOUT_SW_ACLK300_GSCL 653
+#define CLK_MOUT_MCLK_CDREX 654
+#define CLK_MOUT_BPLL 655
+#define CLK_MOUT_MX_MSPLL_CCORE 656
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@@ -239,8 +242,14 @@
#define CLK_DOUT_ACLK300_DISP1 788
#define CLK_DOUT_ACLK300_GSCL 789
#define CLK_DOUT_ACLK400_DISP1 790
+#define CLK_DOUT_PCLK_CDREX 791
+#define CLK_DOUT_SCLK_CDREX 792
+#define CLK_DOUT_ACLK_CDREX1 793
+#define CLK_DOUT_CCLK_DREX0 794
+#define CLK_DOUT_CLK2X_PHY0 795
+#define CLK_DOUT_PCLK_CORE_MEM 796
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 791
+#define CLK_NR_CLKS 797
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h
index c66fc405a79a..842cdc0adff1 100644
--- a/include/dt-bindings/clock/exynos5440.h
+++ b/include/dt-bindings/clock/exynos5440.h
@@ -14,6 +14,8 @@
#define CLK_XTAL 1
#define CLK_ARM_CLK 2
+#define CLK_CPLLA 3
+#define CLK_CPLLB 4
#define CLK_SPI_BAUD 16
#define CLK_PB0_250 17
#define CLK_PR0_250 18