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| author | Thierry Reding <treding@nvidia.com> | 2019-06-24 17:06:13 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-11-11 14:52:53 +0100 |
| commit | 05308d7e7bbc932025f1dafc401c73ce83c6f414 (patch) | |
| tree | 9e8dc75a462b745ccf360d75b6351e863aa0ec8b /include/dt-bindings | |
| parent | clk: tegra: Reimplement SOR clock on Tegra124 (diff) | |
| download | linux-05308d7e7bbc932025f1dafc401c73ce83c6f414.tar.xz linux-05308d7e7bbc932025f1dafc401c73ce83c6f414.zip | |
clk: tegra: Reimplement SOR clocks on Tegra210
In order to allow the display driver to deal uniformly with all SOR
generations, implement the SOR clocks in a way that is compatible with
Tegra186 and later.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 80590c2a117e..44f60623f99b 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -308,7 +308,8 @@ #define TEGRA210_CLK_CLK_OUT_2 278 #define TEGRA210_CLK_CLK_OUT_3 279 #define TEGRA210_CLK_BLINK 280 -/* 281 */ +#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ +#define TEGRA210_CLK_SOR0_OUT 281 #define TEGRA210_CLK_SOR1_OUT 282 /* 283 */ #define TEGRA210_CLK_XUSB_HOST_SRC 284 @@ -390,8 +391,7 @@ #define TEGRA210_CLK_CLK_OUT_3_MUX 358 #define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIB_MUX 360 -#define TEGRA210_CLK_SOR0_LVDS 361 /* deprecated */ -#define TEGRA210_CLK_SOR0_OUT 361 +/* 361 */ #define TEGRA210_CLK_XUSB_SS_DIV2 362 #define TEGRA210_CLK_PLL_M_UD 363 |