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| author | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:14:44 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:20:25 +0100 |
| commit | cdc2d6685c13cc736b4c1c70b184638897c5c46f (patch) | |
| tree | 74c688380be925c6424c31a150813dc5379ea731 /include/dt-bindings | |
| parent | Linux 5.4-rc1 (diff) | |
| download | linux-cdc2d6685c13cc736b4c1c70b184638897c5c46f.tar.xz linux-cdc2d6685c13cc736b4c1c70b184638897c5c46f.zip | |
dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT
Tegra186 and later call this clock SOR0_OUT. Rename it on Tegra124 and
Tegra210 to make the names consistent.
Keep the old name for now to keep device trees buildable until they have
all been converted.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/tegra124-car-common.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 4331f1df6ebe..0c4f5be0a742 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -337,7 +337,8 @@ #define TEGRA124_CLK_CLK_OUT_3_MUX 308 /* 309 */ /* 310 */ -#define TEGRA124_CLK_SOR0_LVDS 311 +#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ +#define TEGRA124_CLK_SOR0_OUT 311 #define TEGRA124_CLK_XUSB_SS_DIV2 312 #define TEGRA124_CLK_PLL_M_UD 313 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 6b77e721f6b1..0bfbfc912c68 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -391,7 +391,8 @@ #define TEGRA210_CLK_CLK_OUT_3_MUX 358 #define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIB_MUX 360 -#define TEGRA210_CLK_SOR0_LVDS 361 +#define TEGRA210_CLK_SOR0_LVDS 361 /* deprecated */ +#define TEGRA210_CLK_SOR0_OUT 361 #define TEGRA210_CLK_XUSB_SS_DIV2 362 #define TEGRA210_CLK_PLL_M_UD 363 |