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| author | Stephen Boyd <sboyd@kernel.org> | 2022-01-12 03:30:35 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-01-12 03:30:35 +0100 |
| commit | 151768f34854e2c9f466ecfc0827742ec5de302b (patch) | |
| tree | b2f69f7e39fbf96f2c0d603e3978abdf11c131fb /include/dt-bindings | |
| parent | Merge branches 'clk-doc', 'clk-renesas', 'clk-at91', 'clk-cleanup' and 'clk-d... (diff) | |
| parent | clk: x86: Fix clk_gate_flags for RV_CLK_GATE (diff) | |
| parent | clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system en... (diff) | |
| parent | Merge tag 'clk-meson-v5.17-1' of https://github.com/BayLibre/clk-meson into c... (diff) | |
| parent | Merge tag 'sunxi-clk-for-5.17-1' of https://git.kernel.org/pub/scm/linux/kern... (diff) | |
| download | linux-151768f34854e2c9f466ecfc0827742ec5de302b.tar.xz linux-151768f34854e2c9f466ecfc0827742ec5de302b.zip | |
Merge branches 'clk-x86', 'clk-stm', 'clk-amlogic' and 'clk-allwinner' into clk-next
* clk-x86:
clk: x86: Fix clk_gate_flags for RV_CLK_GATE
clk: x86: Use dynamic con_id string during clk registration
ACPI: APD: Add a fmw property clk-name
drivers: acpi: acpi_apd: Remove unused device property "is-rv"
x86: clk: clk-fch: Add support for newer family of AMD's SOC
clk: Introduce clk-tps68470 driver
platform/x86: int3472: Deal with probe ordering issues
platform/x86: int3472: Pass tps68470_regulator_platform_data to the tps68470-regulator MFD-cell
platform/x86: int3472: Pass tps68470_clk_platform_data to the tps68470-regulator MFD-cell
platform/x86: int3472: Add get_sensor_adev_and_name() helper
platform/x86: int3472: Split into 2 drivers
platform_data: Add linux/platform_data/tps68470.h file
i2c: acpi: Add i2c_acpi_new_device_by_fwnode() function
i2c: acpi: Use acpi_dev_ready_for_enumeration() helper
ACPI: delay enumeration of devices with a _DEP pointing to an INT3472 device
* clk-stm:
clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system enter shell
* clk-amlogic:
clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB
* clk-allwinner:
clk: sunxi-ng: Add support for the D1 SoC clocks
clk: sunxi-ng: gate: Add macros for gates with fixed dividers
clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw
clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hw
clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw
dt-bindings: clk: Add compatibles for D1 CCUs
clk: sunxi-ng: Allow the CCU core to be built as a module
clk: sunxi-ng: Convert early providers to platform drivers
clk: sunxi-ng: Allow drivers to be built as modules
clk: sunxi-ng: Export symbols used by CCU drivers