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author | Michael Turquette <mturquette@baylibre.com> | 2015-07-24 20:29:53 +0200 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-07-28 20:59:21 +0200 |
commit | 1db92e54f559ef076d6733b78ec6ce49c577390a (patch) | |
tree | aad62e1686d10a79ddc4466810ecf4327c518ae7 /include/dt-bindings | |
parent | clk: allow a clk divider with max divisor when zero (diff) | |
parent | clk: exynos3250: Add cpu clock configuration data and instaniate cpu clock (diff) | |
download | linux-1db92e54f559ef076d6733b78ec6ce49c577390a.tar.xz linux-1db92e54f559ef076d6733b78ec6ce49c577390a.zip |
Merge branch 'v4.3-topic/clk-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next
Diffstat (limited to 'include/dt-bindings')
-rw-r--r-- | include/dt-bindings/clock/exynos3250.h | 1 | ||||
-rw-r--r-- | include/dt-bindings/clock/exynos5250.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index aab088d30199..63d01c15d2b3 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -31,6 +31,7 @@ #define CLK_FOUT_VPLL 4 #define CLK_FOUT_UPLL 5 #define CLK_FOUT_MPLL 6 +#define CLK_ARM_CLK 7 /* Muxes */ #define CLK_MOUT_MPLL_USER_L 16 diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 4273891dc78e..8183d1c237d9 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -21,6 +21,7 @@ #define CLK_FOUT_CPLL 6 #define CLK_FOUT_EPLL 7 #define CLK_FOUT_VPLL 8 +#define CLK_ARM_CLK 9 /* gate for special clocks (sclk) */ #define CLK_SCLK_CAM_BAYER 128 |