diff options
| author | Swapnil Jakhade <sjakhade@cadence.com> | 2021-12-23 07:01:36 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-12-27 12:05:09 +0100 |
| commit | 637feefb8ac53fbe1147edb707b03dc09839fdf5 (patch) | |
| tree | f0e0cd464a6687929a900c824d72f44517bf78ce /include/dt-bindings | |
| parent | phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration (diff) | |
| download | linux-637feefb8ac53fbe1147edb707b03dc09839fdf5.tar.xz linux-637feefb8ac53fbe1147edb707b03dc09839fdf5.zip | |
dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock
Add clock ID for Sierra derived reference clock.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211223060137.9252-15-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/phy/phy-cadence.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h index d55fe6e6b936..0671991208fc 100644 --- a/include/dt-bindings/phy/phy-cadence.h +++ b/include/dt-bindings/phy/phy-cadence.h @@ -18,5 +18,6 @@ /* Sierra */ #define CDNS_SIERRA_PLL_CMNLC 0 #define CDNS_SIERRA_PLL_CMNLC1 1 +#define CDNS_SIERRA_DERIVED_REFCLK 2 #endif /* _DT_BINDINGS_CADENCE_SERDES_H */ |