diff options
| author | Marc Zyngier <maz@kernel.org> | 2022-04-05 20:23:25 +0200 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-05-04 15:09:53 +0200 |
| commit | 94828468a6085e6ae148986d300b634b87f86516 (patch) | |
| tree | 19535d18cdd87541531d26d985f3bb558524b2ab /include/kvm | |
| parent | irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} (diff) | |
| download | linux-94828468a6085e6ae148986d300b634b87f86516.tar.xz linux-94828468a6085e6ae148986d300b634b87f86516.zip | |
KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs
When disabling LPIs, a guest needs to poll GICR_CTLR.RWP in order
to be sure that the write has taken effect. We so far reported it
as 0, as we didn't advertise that LPIs could be turned off the
first place.
Start tracking this state during which LPIs are being disabled,
and expose the 'in progress' state via the RWP bit.
We also take this opportunity to disallow enabling LPIs and programming
GICR_{PEND,PROP}BASER while LPI disabling is in progress, as allowed by
the architecture (UNPRED behaviour).
We don't advertise the feature to the guest yet (which is allowed by
the architecture).
Reviewed-by: Oliver Upton <oupton@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220405182327.205520-3-maz@kernel.org
Diffstat (limited to 'include/kvm')
| -rw-r--r-- | include/kvm/arm_vgic.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index bb30a6803d9f..fdf1c2c322e5 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -347,8 +347,8 @@ struct vgic_cpu { /* Contains the attributes and gpa of the LPI pending tables. */ u64 pendbaser; - - bool lpis_enabled; + /* GICR_CTLR.{ENABLE_LPIS,RWP} */ + atomic_t ctlr; /* Cache guest priority bits */ u32 num_pri_bits; |