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authorPierre Gondois <pierre.gondois@arm.com>2023-04-14 10:14:52 +0200
committerSudeep Holla <sudeep.holla@arm.com>2023-04-14 11:13:39 +0200
commitef9f643a9f8b62bcbcc51f0e0af8599adc2e17ed (patch)
tree81f76375f260f1d9db748114d5d98d91c062f9ca /include/math-emu/op-common.h
parentarch_topology: Remove early cacheinfo error message if -ENOENT (diff)
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cacheinfo: Add use_arch[|_cache]_info field/function
The cache information can be extracted from either a Device Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1 for arm64). The clidr_el1 register is used only if DT/ACPI information is not available. It does not states how caches are shared among CPUs. Add a use_arch_cache_info field/function to identify when the DT/ACPI doesn't provide cache information. Use this information to assume L1 caches are privates and L2 and higher are shared among all CPUs. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20230414081453.244787-5-pierre.gondois@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'include/math-emu/op-common.h')
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