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author | Andrea Parri <parri.andrea@gmail.com> | 2023-08-03 06:27:38 +0200 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-08-09 00:28:37 +0200 |
commit | 4eb2eb1b4c0eb07793c240744843498564a67b83 (patch) | |
tree | 5f1555b7754f49cdf99cc4c39c56778af191fd1f /include/media | |
parent | riscv: Fix CPU feature detection with SMP disabled (diff) | |
download | linux-4eb2eb1b4c0eb07793c240744843498564a67b83.tar.xz linux-4eb2eb1b4c0eb07793c240744843498564a67b83.zip |
riscv,mmio: Fix readX()-to-delay() ordering
Section 2.1 of the Platform Specification [1] states:
Unless otherwise specified by a given I/O device, I/O devices are on
ordering channel 0 (i.e., they are point-to-point strongly ordered).
which is not sufficient to guarantee that a readX() by a hart completes
before a subsequent delay() on the same hart (cf. memory-barriers.txt,
"Kernel I/O barrier effects").
Set the I(nput) bit in __io_ar() to restore the ordering, align inline
comments.
[1] https://github.com/riscv/riscv-platform-specs
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20230803042738.5937-1-parri.andrea@gmail.com
Fixes: fab957c11efe ("RISC-V: Atomic and Locking Code")
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'include/media')
0 files changed, 0 insertions, 0 deletions