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author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2022-05-21 23:37:42 +0200 |
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committer | David S. Miller <davem@davemloft.net> | 2022-05-23 11:39:54 +0200 |
commit | c295f9831f1db12330d6a28a1cb2bd2562535e37 (patch) | |
tree | 7c63c40fbe883a321c0391499d91cb10ebe35824 /include/misc/cxl.h | |
parent | net: dsa: felix: directly call ocelot_port_{set,unset}_dsa_8021q_cpu (diff) | |
download | linux-c295f9831f1db12330d6a28a1cb2bd2562535e37.tar.xz linux-c295f9831f1db12330d6a28a1cb2bd2562535e37.zip |
net: mscc: ocelot: switch from {,un}set to {,un}assign for tag_8021q CPU ports
There is a desire for the felix driver to gain support for multiple
tag_8021q CPU ports, but the current model prevents it.
This is because ocelot_apply_bridge_fwd_mask() only takes into
consideration whether a port is a tag_8021q CPU port, but not whose CPU
port it is.
We need a model where we can have a direct affinity between an ocelot
port and a tag_8021q CPU port. This serves as the basis for multiple CPU
ports.
Declare a "dsa_8021q_cpu" backpointer in struct ocelot_port which
encodes that affinity. Repurpose the "ocelot_set_dsa_8021q_cpu" API to
"ocelot_assign_dsa_8021q_cpu" to express the change of paradigm.
Note that this change makes the first practical use of the new
ocelot_port->index field in ocelot_port_unassign_dsa_8021q_cpu(), where
we need to remove the old tag_8021q CPU port from the reserved VLAN range.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/misc/cxl.h')
0 files changed, 0 insertions, 0 deletions