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authorCatalin Marinas <catalin.marinas@arm.com>2016-07-01 17:53:00 +0200
committerCatalin Marinas <catalin.marinas@arm.com>2016-11-21 19:48:53 +0100
commit4b65a5db362783ab4b04ca1c1d2ad70ed9b0ba2a (patch)
tree56196f2fa7dbe5a41061b1aed297704ef7e2bbea /include/pcmcia
parentarm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro (diff)
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arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1
This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset. Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros. Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Kees Cook <keescook@chromium.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'include/pcmcia')
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