diff options
| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2021-10-12 13:40:36 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2021-10-13 02:35:17 +0200 |
| commit | 52849bcf0029ccc553be304e4f804938a39112e2 (patch) | |
| tree | 164fb20ac0bac33fbf83ae0139fc9953db90a897 /include/soc/mscc/ocelot_ptp.h | |
| parent | net: mscc: ocelot: make use of all 63 PTP timestamp identifiers (diff) | |
| download | linux-52849bcf0029ccc553be304e4f804938a39112e2.tar.xz linux-52849bcf0029ccc553be304e4f804938a39112e2.zip | |
net: mscc: ocelot: avoid overflowing the PTP timestamp FIFO
PTP packets with 2-step TX timestamp requests are matched to packets
based on the egress port number and a 6-bit timestamp identifier.
All PTP timestamps are held in a common FIFO that is 128 entry deep.
This patch ensures that back-to-back timestamping requests cannot exceed
the hardware FIFO capacity. If that happens, simply send the packets
without requesting a TX timestamp to be taken (in the case of felix,
since the DSA API has a void return code in ds->ops->port_txtstamp) or
drop them (in the case of ocelot).
I've moved the ts_id_lock from a per-port basis to a per-switch basis,
because we need separate accounting for both numbers of PTP frames in
flight. And since we need locking to inc/dec the per-switch counter,
that also offers protection for the per-port counter and hence there is
no reason to have a per-port counter anymore.
Fixes: 4e3b0468e6d7 ("net: mscc: PTP Hardware Clock (PHC) support")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include/soc/mscc/ocelot_ptp.h')
| -rw-r--r-- | include/soc/mscc/ocelot_ptp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/soc/mscc/ocelot_ptp.h b/include/soc/mscc/ocelot_ptp.h index 6e54442b49ad..f085884b1fa2 100644 --- a/include/soc/mscc/ocelot_ptp.h +++ b/include/soc/mscc/ocelot_ptp.h @@ -14,6 +14,7 @@ #include <soc/mscc/ocelot.h> #define OCELOT_MAX_PTP_ID 63 +#define OCELOT_PTP_FIFO_SIZE 128 #define PTP_PIN_CFG_RSZ 0x20 #define PTP_PIN_TOD_SEC_MSB_RSZ PTP_PIN_CFG_RSZ |