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| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2022-05-21 23:37:43 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-05-23 11:39:55 +0200 |
| commit | a4e044dc4c5b1e03f4195224c47108dc44122917 (patch) | |
| tree | 41b0ac849a21733f9e405d2623c0f77db876ea5b /include/soc/mscc/ocelot_vcap.h | |
| parent | net: mscc: ocelot: switch from {,un}set to {,un}assign for tag_8021q CPU ports (diff) | |
| download | linux-a4e044dc4c5b1e03f4195224c47108dc44122917.tar.xz linux-a4e044dc4c5b1e03f4195224c47108dc44122917.zip | |
net: dsa: felix: tag_8021q preparation for multiple CPU ports
Update the VCAP filters to support multiple tag_8021q CPU ports.
TX works using a filter for VLAN ID on the ingress of the CPU port, with
a redirect and a VLAN pop action. This can be updated trivially by
amending the ingress port mask of this rule to match on all tag_8021q
CPU ports.
RX works using a filter for ingress port on the egress of the CPU port,
with a VLAN push action. Here we need to replicate these filters for
each tag_8021q CPU port, and let them all have the same action.
This means that the OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN() cookie needs to
encode a unique value for every {user port, CPU port} pair it's given.
Do this by encoding the CPU port in the upper 16 bits of the cookie, and
the user port in the lower 16 bits.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/soc/mscc/ocelot_vcap.h')
| -rw-r--r-- | include/soc/mscc/ocelot_vcap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/soc/mscc/ocelot_vcap.h b/include/soc/mscc/ocelot_vcap.h index de26c992f821..c601a4598b0d 100644 --- a/include/soc/mscc/ocelot_vcap.h +++ b/include/soc/mscc/ocelot_vcap.h @@ -11,7 +11,7 @@ /* Cookie definitions for private VCAP filters installed by the driver. * Must be unique per VCAP block. */ -#define OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port) (port) +#define OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream) ((upstream) << 16 | (port)) #define OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port) (port) #define OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port) (port) #define OCELOT_VCAP_IS2_MRP_REDIRECT(ocelot, port) ((ocelot)->num_phys_ports + (port)) |