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| author | Ioana Ciornei <ioana.ciornei@nxp.com> | 2021-10-15 11:01:24 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-10-15 15:32:40 +0200 |
| commit | ed1d2143fee53755ec601eb4d48a337a93933f71 (patch) | |
| tree | 4a730ca59c0a63de840a68a96d75311b2a0e2243 /include/soc | |
| parent | soc: fsl: dpio: extract the QBMAN clock frequency from the attributes (diff) | |
| download | linux-ed1d2143fee53755ec601eb4d48a337a93933f71.tar.xz linux-ed1d2143fee53755ec601eb4d48a337a93933f71.zip | |
soc: fsl: dpio: add support for irq coalescing per software portal
In DPAA2 based SoCs, the IRQ coalesing support per software portal has 2
configurable parameters:
- the IRQ timeout period (QBMAN_CINH_SWP_ITPR): how many 256 QBMAN
cycles need to pass until a dequeue interrupt is asserted.
- the IRQ threshold (QBMAN_CINH_SWP_DQRR_ITR): how many dequeue
responses in the DQRR ring would generate an IRQ.
Add support for setting up and querying these IRQ coalescing related
parameters.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/fsl/dpaa2-io.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/soc/fsl/dpaa2-io.h b/include/soc/fsl/dpaa2-io.h index 041ebf7d804c..9bff280fe8f4 100644 --- a/include/soc/fsl/dpaa2-io.h +++ b/include/soc/fsl/dpaa2-io.h @@ -131,4 +131,8 @@ int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid, u32 *fcnt, u32 *bcnt); int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, u32 *num); + +int dpaa2_io_set_irq_coalescing(struct dpaa2_io *d, u32 irq_holdoff); +void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff); + #endif /* __FSL_DPAA2_IO_H */ |