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| author | Jeeja KP <jeeja.kp@intel.com> | 2015-12-18 10:41:59 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-01-10 13:02:30 +0100 |
| commit | a9c48f7f5906d02d4ec4aa50b1c20fccbce53eec (patch) | |
| tree | 845f455a73f44b45c1f6d075ce73ab76b0363677 /include/sound/hda_register.h | |
| parent | ALSA: hdac: structure definition for ext_dma_params (diff) | |
| download | linux-a9c48f7f5906d02d4ec4aa50b1c20fccbce53eec.tar.xz linux-a9c48f7f5906d02d4ec4aa50b1c20fccbce53eec.zip | |
ALSA: hdac: Add support for hda DMA Resume capability
Skylake sports new capability of DMA resume, DRSM where we can
resume the DMA. This capability is defined by presence of
AZX_DRSM_CAP_ID.
If this capability is present, we use this capability.
So we add:
snd_hdac_ext_stream_drsm_enable() - DMA resume caps
snd_hdac_ext_stream_set_dpibr() - set the DMA position
snd_hdac_ext_stream_set_lpib() - set the lpib
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/sound/hda_register.h')
| -rw-r--r-- | include/sound/hda_register.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 2ae8812d7b1a..28ac1f9a18ac 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -230,6 +230,15 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_MLCTL_SPA (1<<16) #define AZX_MLCTL_CPA 23 + +/* registers for DMA Resume Capability Structure */ +#define AZX_DRSM_CAP_ID 0x5 +#define AZX_REG_DRSM_CTL 0x4 +/* Base used to calculate the iterating register offset */ +#define AZX_DRSM_BASE 0x08 +/* Interval used to calculate the iterating register offset */ +#define AZX_DRSM_INTERVAL 0x08 + /* * helpers to read the stream position */ |