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| author | Mengdong Lin <mengdong.lin@intel.com> | 2015-05-19 16:29:30 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2015-05-20 06:16:36 +0200 |
| commit | 98d8fc6c5d3652e91c61d78941e0fa6f94771d67 (patch) | |
| tree | 31f5d9ce478f828686fb848b66bebc664c51898f /include/sound/hda_register.h | |
| parent | ALSA: hda - Fix NULL dereference from CA0132 DSP loader (diff) | |
| download | linux-98d8fc6c5d3652e91c61d78941e0fa6f94771d67.tar.xz linux-98d8fc6c5d3652e91c61d78941e0fa6f94771d67.zip | |
ALSA: hda - Move hda_i915.c from sound/pci/hda to sound/hda
The file is moved to hda core and renamed to hdac_i915.c, so can be used
by both legacy HDA driver and new Skylake audio driver.
- Add snd_hdac_ prefix to the public APIs.
- The i915 audio component is moved to core bus and dynamically allocated.
- A static pointer hdac_acomp is used to help bind/unbind callbacks to get
this component, because the sound card's private_data is used by the azx
chip pointer, which is a legacy structure. It could be removed if private
_data changes to some core structure which can be extended to find the
bus.
- snd_hdac_get_display_clk() is added to get the display core clock for
HSW/BDW.
- haswell_set_bclk() is moved to hda_intel.c because it needs to write the
controller registers EM4/EM5, and only legacy HD-A needs it for HSW/BDW.
- Move definition of HSW/BDW-specific registers EM4/EM5 to hda_register.h
and rename them to HSW_EM4/HSW_EM5, because other HD-A controllers have
different layout for the extended mode registers.
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'include/sound/hda_register.h')
| -rw-r--r-- | include/sound/hda_register.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 4f6d3fce6ee6..0c7536e30fa4 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -84,6 +84,10 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_SD_BDLPL 0x18 #define AZX_REG_SD_BDLPU 0x1c +/* Haswell/Broadwell display HD-A controller Extended Mode registers */ +#define AZX_REG_HSW_EM4 0x100c +#define AZX_REG_HSW_EM5 0x1010 + /* PCI space */ #define AZX_PCIREG_TCSEL 0x44 |