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authorMark Brown <broonie@kernel.org>2023-08-23 20:54:43 +0200
committerMark Brown <broonie@kernel.org>2023-08-23 20:54:43 +0200
commitfd53c16b392dd4e1d6997a0e2425895d4cb29ff8 (patch)
tree336a0b2b20c6d59e22113140b02c9344f3cdf650 /include/sound
parentASoC: audio-graph-card2: add comment for format property (diff)
parentASoC: rsnd: setup BRGCKR/BRRA/BRRB on rsnd_adg_clk_control() (diff)
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ASoC: rsnd: tidyup ADG
Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>: Renesas Sound has ADG for clock control. Basically it needs accurately divisible external input clock. But sometimes sometimes it doesn't have to be accurate for some reason. We can use ADG clk_i for such case. It came from CPG as very high rate clock, but is not accurately divisible for 48kHz/44.1kHz rate, but enough for approximate rate. This patch set support such use case.
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