diff options
| author | Mika Kahola <mika.kahola@intel.com> | 2022-04-11 16:34:04 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-04-12 11:39:45 +0200 |
| commit | 9035039e1ed691cd893777a42e048003a2f349d6 (patch) | |
| tree | dbb9c81b432a5cb417da085c374e5d274ba2c715 /include/uapi/drm/drm_fourcc.h | |
| parent | drm/i915/dg2: Add support for DG2 render and media compression (diff) | |
| download | linux-9035039e1ed691cd893777a42e048003a2f349d6.tar.xz linux-9035039e1ed691cd893777a42e048003a2f349d6.zip | |
drm/fourcc: Introduce format modifier for DG2 clear color
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
v2:
Display version is fixed. [Imre]
KDoc is enhanced for cc modifier. [Nanley & Lionel]
v3:
Split out the modifier addition to a separate patch.
Clarify the modifier layout description.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220411143405.1073845-4-imre.deak@intel.com
Diffstat (limited to 'include/uapi/drm/drm_fourcc.h')
| -rw-r--r-- | include/uapi/drm/drm_fourcc.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 4a5117715db3..e5074162bcdd 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -606,6 +606,20 @@ extern "C" { #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) /* + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. + * + * The main surface is Tile 4 and at plane index 0. The CCS data is stored + * outside of the GEM object in a reserved memory area dedicated for the + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The + * main surface pitch is required to be a multiple of four Tile 4 widths. The + * clear color is stored at plane index 1 and the pitch should be ignored. The + * format of the 256 bits of clear color data matches the one used for the + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description + * for details. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) + +/* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * * Macroblocks are laid in a Z-shape, and each pixel data is following the |