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| author | Matt Roper <matthew.d.roper@intel.com> | 2022-04-28 06:19:25 +0200 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-04-29 23:30:27 +0200 |
| commit | ecf8eca51f33dbfddcc23902bdee65c17587247c (patch) | |
| tree | 62f54bb7678bc6bdc3b74c82925874b9aa3a280b /include/uapi/drm/i915_drm.h | |
| parent | drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation (diff) | |
| download | linux-ecf8eca51f33dbfddcc23902bdee65c17587247c.tar.xz linux-ecf8eca51f33dbfddcc23902bdee65c17587247c.zip | |
drm/i915/xehp: Add compute engine ABI
We're now ready to start exposing compute engines to userspace.
v2:
- Move kerneldoc for other engine classes to a separate patch. (Andi)
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Szymon Morek <szymon.morek@intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com> # mesa anvil & iris
Link: https://patchwork.freedesktop.org/patch/msgid/20220428041926.1483683-4-matthew.d.roper@intel.com
Diffstat (limited to 'include/uapi/drm/i915_drm.h')
| -rw-r--r-- | include/uapi/drm/i915_drm.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index ec000fc6c879..a2def7b27009 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -203,6 +203,15 @@ enum drm_i915_gem_engine_class { */ I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, + /** + * @I915_ENGINE_CLASS_COMPUTE: + * + * Compute engines support a subset of the instructions available + * on render engines: compute engines support Compute (GPGPU) and + * programmable media workloads, but do not support the 3D pipeline. + */ + I915_ENGINE_CLASS_COMPUTE = 4, + /* Values in this enum should be kept compact. */ /** |