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| author | Jason Gunthorpe <jgg@nvidia.com> | 2021-03-04 14:05:01 +0100 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2021-03-12 01:20:37 +0100 |
| commit | 7610ab57de5616631b664ea31c11bad527810391 (patch) | |
| tree | e86407345a00ef5e2bb2a7ee81c2e42b50cf3e89 /include/uapi/rdma | |
| parent | IB/core: Split uverbs_get_const/default to consider target type (diff) | |
| download | linux-7610ab57de5616631b664ea31c11bad527810391.tar.xz linux-7610ab57de5616631b664ea31c11bad527810391.zip | |
RDMA/mlx5: Allow larger pages in DevX umem
The umem DMA list calculation was locked at 4k pages due to confusion
around how this API works and is used when larger pages are present.
The conclusion is:
- umem's cannot extend past what is mapped into the process, so creating
a lage page size and referring to a sub-range is not allowed
- umem's must always have a page offset of zero, except for sub PAGE_SIZE
umems
- The feature of umem_offset to create multiple objects inside a umem
is buggy and isn't used anyplace. Thus we can assume all users of the
current API have umem_offset == 0 as well
Provide a new page size calculator that limits the DMA list to the VA
range and enforces umem_offset == 0.
Allow user space to specify the page sizes which it can accept, this
bitmap must be derived from the intended use of the umem, based on
per-usage HW limitations.
Link: https://lore.kernel.org/r/20210304130501.1102577-4-leon@kernel.org
Signed-off-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'include/uapi/rdma')
| -rw-r--r-- | include/uapi/rdma/mlx5_user_ioctl_cmds.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/rdma/mlx5_user_ioctl_cmds.h b/include/uapi/rdma/mlx5_user_ioctl_cmds.h index 3fd9b380a091..3f0bc7597ba7 100644 --- a/include/uapi/rdma/mlx5_user_ioctl_cmds.h +++ b/include/uapi/rdma/mlx5_user_ioctl_cmds.h @@ -154,6 +154,7 @@ enum mlx5_ib_devx_umem_reg_attrs { MLX5_IB_ATTR_DEVX_UMEM_REG_LEN, MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, + MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP, }; enum mlx5_ib_devx_umem_dereg_attrs { |