diff options
| author | John Crispin <blogic@openwrt.org> | 2014-10-16 21:48:21 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-11-06 23:57:18 +0100 |
| commit | 9b8777e3473e31b2aabd669e5f34866d4a3afb6a (patch) | |
| tree | 151015ce45bd2bc3284b1bcbebbedb462f7e690d /include/uapi | |
| parent | tty: serial: omap: Increase max consoles and add check to prevent crash (diff) | |
| download | linux-9b8777e3473e31b2aabd669e5f34866d4a3afb6a.tar.xz linux-9b8777e3473e31b2aabd669e5f34866d4a3afb6a.zip | |
serial: of: add a PORT_RT2880 definition
The Ralink RT2880 SoC and its successors have an internal 8250 core. This core
needs the same quirks applied as the AMD AU1xxx uart. In addition to these
quirks, the ports memory region is only 0x100 unlike the AU1xxx which has a
size of 0x1000.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/linux/serial_core.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 16ad8521af6a..c17218094f18 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -54,7 +54,8 @@ #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */ #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ -#define PORT_MAX_8250 28 /* max port ID */ +#define PORT_RT2880 29 /* Ralink RT2880 internal UART */ +#define PORT_MAX_8250 29 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed |