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authorLucas Stach <l.stach@pengutronix.de>2017-04-05 15:19:09 +0200
committerShawn Guo <shawnguo@kernel.org>2017-04-07 14:47:34 +0200
commit44c43c98213fb123819c67c128a5d6c9a9a12280 (patch)
treedeb520a07a0607cdb4c6220fad7481bcd08db8cf /include/video
parentdt-bindings: imx-gpc: add i.MX6 QuadPlus compatible (diff)
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soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
On i.MX6QP, due to hardware erratum ERR009619, the PRE clocks may be stalled during the power up sequencing of the PU power domain. As this may lead to a complete loss of display output, the recommended workaround is to keep the PU domain enabled during normal system operation. Implement this by rejecting the domain power down request on the affected SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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