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author | Vinod Koul <vinod.koul@linux.intel.com> | 2011-09-02 13:13:44 +0200 |
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committer | Vinod Koul <vinod.koul@intel.com> | 2011-09-02 13:13:44 +0200 |
commit | 8516f52fa497b37eb3d5e58d34e61a41ae0a553a (patch) | |
tree | b73175b134d36bea303d2f181ae89a448c2add81 /include | |
parent | Linux 3.1-rc4 (diff) | |
parent | dmaengine i.MX SDMA: use request_firmware_nowait (diff) | |
download | linux-8516f52fa497b37eb3d5e58d34e61a41ae0a553a.tar.xz linux-8516f52fa497b37eb3d5e58d34e61a41ae0a553a.zip |
Merge branch 'next' into v3.1-rc4
Fixed trivial conflicts in drivers/dma/amba-pl08x.c
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/amba/pl08x.h | 14 | ||||
-rw-r--r-- | include/linux/dmaengine.h | 13 |
2 files changed, 23 insertions, 4 deletions
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h index e6e28f37d8ec..a22662c93981 100644 --- a/include/linux/amba/pl08x.h +++ b/include/linux/amba/pl08x.h @@ -47,6 +47,9 @@ enum { * @muxval: a number usually used to poke into some mux regiser to * mux in the signal to this channel * @cctl_opt: default options for the channel control register + * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave + * channels. Fill with 'true' if peripheral should be flow controller. Direction + * will be selected at Runtime. * @addr: source/target address in physical memory for this DMA channel, * can be the address of a FIFO register for burst requests for example. * This can be left undefined if the PrimeCell API is used for configuring @@ -65,6 +68,7 @@ struct pl08x_channel_data { int max_signal; u32 muxval; u32 cctl; + bool device_fc; dma_addr_t addr; bool circular_buffer; bool single; @@ -77,13 +81,11 @@ struct pl08x_channel_data { * @addr: current address * @maxwidth: the maximum width of a transfer on this bus * @buswidth: the width of this bus in bytes: 1, 2 or 4 - * @fill_bytes: bytes required to fill to the next bus memory boundary */ struct pl08x_bus_data { dma_addr_t addr; u8 maxwidth; u8 buswidth; - size_t fill_bytes; }; /** @@ -105,8 +107,16 @@ struct pl08x_phy_chan { /** * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor + * @tx: async tx descriptor + * @node: node for txd list for channels + * @src_addr: src address of txd + * @dst_addr: dst address of txd + * @len: transfer len in bytes + * @direction: direction of transfer * @llis_bus: DMA memory address (physical) start for the LLIs * @llis_va: virtual memory address start for the LLIs + * @cctl: control reg values for current txd + * @ccfg: config reg values for current txd */ struct pl08x_txd { struct dma_async_tx_descriptor tx; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 8fbf40e0713c..ace51af4369f 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -24,8 +24,7 @@ #include <linux/device.h> #include <linux/uio.h> #include <linux/dma-direction.h> - -struct scatterlist; +#include <linux/scatterlist.h> /** * typedef dma_cookie_t - an opaque DMA cookie @@ -519,6 +518,16 @@ static inline int dmaengine_slave_config(struct dma_chan *chan, (unsigned long)config); } +static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( + struct dma_chan *chan, void *buf, size_t len, + enum dma_data_direction dir, unsigned long flags) +{ + struct scatterlist sg; + sg_init_one(&sg, buf, len); + + return chan->device->device_prep_slave_sg(chan, &sg, 1, dir, flags); +} + static inline int dmaengine_terminate_all(struct dma_chan *chan) { return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); |