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authorAlex Williamson <alex.williamson@redhat.com>2013-12-18 00:43:57 +0100
committerBjorn Helgaas <bhelgaas@google.com>2013-12-18 01:49:39 +0100
commit274127a1fdbad3c0d64e813521f4a0ef96cfc70e (patch)
tree72c5702de4cfcb7337550f355af46f568c448022 /include
parentPCI: Add Virtual Channel to save/restore support (diff)
downloadlinux-274127a1fdbad3c0d64e813521f4a0ef96cfc70e.tar.xz
linux-274127a1fdbad3c0d64e813521f4a0ef96cfc70e.zip
PCI: Rename PCI_VC_PORT_REG1/2 to PCI_VC_PORT_CAP1/2
These are set of two capability registers, it's pretty much given that they're registers, so reflect their purpose in the name. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/pci_regs.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 5eefacd93e18..d0160cc83fcf 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -677,15 +677,15 @@
#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
/* Virtual Channel */
-#define PCI_VC_PORT_REG1 4
-#define PCI_VC_REG1_EVCC 0x00000007 /* extended VC count */
-#define PCI_VC_REG1_LPEVCC 0x00000070 /* low prio extended VC count */
-#define PCI_VC_REG1_ARB_SIZE 0x00000c00
-#define PCI_VC_PORT_REG2 8
-#define PCI_VC_REG2_32_PHASE 0x00000002
-#define PCI_VC_REG2_64_PHASE 0x00000004
-#define PCI_VC_REG2_128_PHASE 0x00000008
-#define PCI_VC_REG2_ARB_OFF 0xff000000
+#define PCI_VC_PORT_CAP1 4
+#define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */
+#define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */
+#define PCI_VC_CAP1_ARB_SIZE 0x00000c00
+#define PCI_VC_PORT_CAP2 8
+#define PCI_VC_CAP2_32_PHASE 0x00000002
+#define PCI_VC_CAP2_64_PHASE 0x00000004
+#define PCI_VC_CAP2_128_PHASE 0x00000008
+#define PCI_VC_CAP2_ARB_OFF 0xff000000
#define PCI_VC_PORT_CTRL 12
#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001
#define PCI_VC_PORT_STATUS 14