diff options
| author | Padmavathi Venna <padma.v@samsung.com> | 2015-01-13 12:27:41 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-01-15 15:11:40 +0100 |
| commit | ee74b56ab2f72c088fc5a8ba3797ef6a452d692a (patch) | |
| tree | 684418362c9eb12c633ec4eeb645ed452e67482b /include | |
| parent | clk: samsung: exynos7: add gate clock for DMA block (diff) | |
| download | linux-ee74b56ab2f72c088fc5a8ba3797ef6a452d692a.tar.xz linux-ee74b56ab2f72c088fc5a8ba3797ef6a452d692a.zip | |
clk: samsung: exynos7: add clocks for SPI block
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/exynos7-clk.h | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 05e2a47bcb96..75c5888068b2 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -28,7 +28,12 @@ #define CLK_SCLK_UART1 4 #define CLK_SCLK_UART2 5 #define CLK_SCLK_UART3 6 -#define TOP0_NR_CLK 7 +#define CLK_SCLK_SPI0 7 +#define CLK_SCLK_SPI1 8 +#define CLK_SCLK_SPI2 9 +#define CLK_SCLK_SPI3 10 +#define CLK_SCLK_SPI4 11 +#define TOP0_NR_CLK 12 /* TOP1 */ #define DOUT_ACLK_FSYS1_200 1 @@ -72,7 +77,17 @@ #define PCLK_HSI2C6 9 #define PCLK_HSI2C7 10 #define PCLK_HSI2C8 11 -#define PERIC1_NR_CLK 12 +#define PCLK_SPI0 12 +#define PCLK_SPI1 13 +#define PCLK_SPI2 14 +#define PCLK_SPI3 15 +#define PCLK_SPI4 16 +#define SCLK_SPI0 17 +#define SCLK_SPI1 18 +#define SCLK_SPI2 19 +#define SCLK_SPI3 20 +#define SCLK_SPI4 21 +#define PERIC1_NR_CLK 22 /* PERIS */ #define PCLK_CHIPID 1 |