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author | Ken Wang <Qingqing.Wang@amd.com> | 2015-06-03 11:36:54 +0200 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2015-06-04 03:04:01 +0200 |
commit | 32bf7106e072b59cade754062ed86023309f50d9 (patch) | |
tree | 31ef93eb35ed310e9a9970a4d16a9f62597fd195 /include | |
parent | drm/amdgpu: add hdp flush for gfx8 compute ring (diff) | |
download | linux-32bf7106e072b59cade754062ed86023309f50d9.tar.xz linux-32bf7106e072b59cade754062ed86023309f50d9.zip |
drm/amdgpu add max_memory_clock for interface query (v2)
Add a query for the max memory clock.
v2: handle the dpm enabled case properly
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewd-by: Jammy Zhou <Jammy.Zhou@amd.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/uapi/drm/amdgpu_drm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index cd54891b1d5c..420c762f2ed7 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -553,6 +553,7 @@ struct drm_amdgpu_info_device { uint32_t num_shader_arrays_per_engine; uint32_t gpu_counter_freq; /* in KHz */ uint64_t max_engine_clock; /* in KHz */ + uint64_t max_memory_clock; /* in KHz */ /* cu information */ uint32_t cu_active_number; uint32_t cu_ao_mask; |