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authorLinus Torvalds <torvalds@linux-foundation.org>2019-04-28 19:00:45 +0200
committerLinus Torvalds <torvalds@linux-foundation.org>2019-04-28 19:00:45 +0200
commit14f974d7f0f1f93d8c35f496ae774ba0f1b3389a (patch)
treef91018a260c8090311ef4cfde609a9487967daab /include
parentMerge tag 'dmaengine-fix-5.1-rc7' of git://git.infradead.org/users/vkoul/slav... (diff)
parentRDMA/hns: Bugfix for mapping user db (diff)
downloadlinux-14f974d7f0f1f93d8c35f496ae774ba0f1b3389a.tar.xz
linux-14f974d7f0f1f93d8c35f496ae774ba0f1b3389a.zip
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
Pull rdma fixes from Jason Gunthorpe: "One core bug fix and a few driver ones - FRWR memory registration for hfi1/qib didn't work with with some iovas causing a NFSoRDMA failure regression due to a fix in the NFS side - A command flow error in mlx5 allowed user space to send a corrupt command (and also smash the kernel stack we've since learned) - Fix a regression and some bugs with device hot unplug that was discovered while reviewing Andrea's patches - hns has a failure if the user asks for certain QP configurations" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: RDMA/hns: Bugfix for mapping user db RDMA/ucontext: Fix regression with disassociate RDMA/mlx5: Use rdma_user_map_io for mapping BAR pages RDMA/mlx5: Do not allow the user to write to the clock page IB/mlx5: Fix scatter to CQE in DCT QP creation IB/rdmavt: Fix frwr memory registration
Diffstat (limited to 'include')
-rw-r--r--include/uapi/rdma/mlx5-abi.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/rdma/mlx5-abi.h b/include/uapi/rdma/mlx5-abi.h
index 87b3198f4b5d..f4d4010b7e3e 100644
--- a/include/uapi/rdma/mlx5-abi.h
+++ b/include/uapi/rdma/mlx5-abi.h
@@ -238,6 +238,7 @@ enum mlx5_ib_query_dev_resp_flags {
MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
+ MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
};
enum mlx5_ib_tunnel_offloads {