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| author | Krzysztof Kozlowski <krzk@kernel.org> | 2017-01-31 20:36:52 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2017-01-31 20:36:52 +0100 |
| commit | 67707c78f592590c83604d37e709f2e5218a5ac0 (patch) | |
| tree | 10c6d9c1a0005697f637b853d68b5591198ac5c5 /include | |
| parent | arm64: dts: exynos: Add clocks to Exynos5433 LPASS module (diff) | |
| parent | clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates (diff) | |
| download | linux-67707c78f592590c83604d37e709f2e5218a5ac0.tar.xz linux-67707c78f592590c83604d37e709f2e5218a5ac0.zip | |
Merge tag 'clk-v4.11-samsung-dphy' of git://linuxtv.org/snawrocki/samsung into next/dt64
Exporting clocks for MIPI DSI DPHY and the display PLL
frequency list update for Exynos5433 SoC.
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/exynos5433.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 4fa6bb2136e3..be39d23e6a32 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -771,7 +771,10 @@ #define CLK_PCLK_DECON 113 -#define DISP_NR_CLK 114 +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 + +#define DISP_NR_CLK 116 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 |